4-Bit AC Nano-Processor

Design for Self-Powered Biomedical and Smart Dust Applications

A revolutionary adiabatic processor eliminating RF-to-DC rectifiers and large storage capacitors, enabling self-powered IoT nodes and smart dust.

Project Description

The development of a 4-bit AC nano-processor represents a significant shift in the design of self-powered IoT nodes and "smart dust." Traditional wireless power transfer (WPT) systems are hindered by the inefficiency of RF-to-DC rectifiers and the substantial area required for storage capacitors. The AC-logic family utilizes the phase of the signal to represent logic states 0∘ for High and 180∘ for Low while the QRF only logic utilizes quadrature (I and Q) signals to manage timing phases such as pre-charge, hold, and evaluate. This "rectifier-less" architecture eliminates the most power-hungry components of conventional designs.

Experimental validation of these logic families across different CMOS nodes demonstrates their suitability for complex processing tasks. In 65 nm CMOS, the fundamental AC gates (NOT, NAND, and NOR) consume as little as 8.2 nW to 20.8 nW.

The integration of these AC and QRF components into a 4-bit nano-processor provides a robust framework for next-generation implantable bio-medical devices and autonomous sensors. By leveraging the inherent adiabatic nature of the proposed logic cells, the processor can derive both its power and data synchronization directly from transmitted RF field. This design not only simplifies the complexity of single chip wirelessly powered applications but also ensures long-term operation in environments where battery replacement is impossible. The successful measurement of these fabricated single cell design confirms that logic information can be reliably processed in the phase domain, paving the way for fully functional, battery-free nano-computing.

Here in this project we aim to make the 4-bit ultra-low power nano-prcessor based on these AC-Cells. The schematic work has been done for one version, and US patent filed. The next step is the refinement of the schematic of the layout and tapeout.

AC-Logic & QRF Families

The methodology applies adiabatic CMOS logic to process sinusoidal signals with minimal power dissipation. We exploit phase differences using two distinct approaches:

AC Logic (180°)

Uses 180° out-of-phase differential sinusoids. The instantaneous voltage difference defines a valid logic evaluation region.

Quadrature RF (90°)

Employs 90° QRF signals to create distinct precharge, hold, and evaluation phases, avoiding standard DC generation.

Aspect AC Logic Quadrature RF
Type Two Sinusoids Signal 180° out of phase Quadrature RF signals (I & Q) 90° apart
Topology Static CMOS Structure (PUN + PDN) Dynamic Logic Architecture
Regions Valid, Invalid Precharge, Hold, Evaluate
Isolation Series PMOS with body-biasing technique Double Isolation Transistor
Efficiency 53.9% Energy Saved at System Level 60% Less Power Consumption

Results & Future Work

  • Verified Cells: Fundamental logic cells (inverters, NAND, NOR, XOR, DFF) for both approaches have been designed and verified in 65 nm CMOS.
  • Architecture Basis: The design follows the 4-Bit Intel4004 Architecture, featuring memory, ALU, stack, and register multiplexers.
  • Current Status: The schematic work has been done for one version, and US patent filed. The next step is the refinement of the schematic, layout, and tapeout.
  • Fabrication: Physical fabrication and experimental validation of the rectifier-less architecture in 65 nm CMOS are planned.

Project Supervisors

Rashad Ramzan

Rashad Ramzan

Professor
Hassan Saif

Hassan Saif

Professor
Khurram Javed

Khurram Javed

Professor

Engineering Team

Humbal Hammad

Humbal Hammad

IC Design Engineer
Shahrukh Hussain

Shahrukh Hussain

IC Design Engineer
Ejaz Ahmed

Ejaz Ahmed

IC Design Engineer
Uzair Sharif

Uzair Sharif

IC Design Engineer
Ahsan Zia

Ahsan Zia

IC Design Engineer
Junaid Razzaq

Junaid Razzaq

IC Design Engineer
Muazzam Iftikhar

Muazzam Iftikhar

IC Design Engineer
Muhammad Arsalan

Muhammad Arsalan

IC Design Engineer
Ajmal Khan

Ajmal Khan

IC Design Engineer
Hadeesa Mehboob

Hadeesa Mehboob

IC Design Engineer

References

  1. R. Ramzan, A. Beg, S. A. Jawed, F. Khan, M. Aaquib, and M. Junaid, "Quadrature RF-Only Logic Family for Single-Chip Self-Powered Transceivers," National University of Computer and Emerging Sciences (FAST-NU), Islamabad, Pakistan.
  2. "AC-Logic Family for Wireless Powered Smart Dust and IoT Applications," Proceedings of the 36th IEEE International System-on-Chip Conference (SOCC), 2023.
  3. S. B. Baker, W. Xiang and L. Atkinson, "Internet of Things for Smart Healthcare: Technologies, Challenges, and Opportunities," IEEE Access, vol. 5, pp. 26521-26544, 2017.
  4. W. Arshad, R. Ramzan, A. Beg and N. Bastaki, "Comparison and design of VCOs for ultra-low power CMOS temperature sensors," IEEE International Conference on Communications, Signal Processing, and their Applications (ICCSPA), 2015.
  5. J. Wenck, R. Amirtharajah, J. Collier, and J. Siebert, "AC power supply circuits for energy harvesting," IEEE Symposium on VLSI Circuits, pp. 92-93, 2007.